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| ICX039DLA Diagonal 8mm (Type 1/2) CCD Image Sensor for CCIR Black-and-White Video Cameras Description The ICX039DLA is an interline CCD solid-state image sensor suitable for CCIR black-and-white video cameras with a diagonal 8mm (Type 1/2) system. Smear, sensitivity, D-range, S/N and other characteristics have been greatly improved compared with the ICX039BLA. High sensitivity and low dark current are achieved through the adoption of HAD (Hole-Accumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable charge-storage time. This chip is compatible with and can replace the ICX039BLA. 20 pin DIP (Cer-DIP) Pin 1 2 V Features * Low smear (-20dB compared with the ICX039BLA) 3 40 H Pin 11 * High sensitivity (+3.0dB compared with the ICX039BLA) * High D range (+2.5dB compared with the ICX039BLA) Optical black position * High S/N (Top View) * High resolution and low dark current * Excellent antiblooming characteristics * Continuous variable-speed shutter * Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) * Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) * Horizontal register: 5V drive Device Structure * Interline CCD image sensor * Image size: Diagonal 8mm (Type 1/2) * Number of effective pixels: 752 (H) x 582 (V) approx. 440K pixels * Total number of pixels: 795 (H) x 596 (V) approx. 470K pixels * Chip size: 7.95mm (H) x 6.45mm (V) * Unit cell size: 8.6m (H) x 8.3m (V) * Optical black: Horizontal (H) direction : Front 3 pixels, rear 40 pixels Vertical (V) direction : Front 12 pixels, rear 2 pixels * Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) * Substrate material: Silicon 12 Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95714C99 ICX039DLA Block Diagram and Pin Configuration (Top View) VOUT GND GND VDD SUB V1 V2 V3 2 10 9 8 7 6 5 4 3 Vertical Register Note) Horizontal Register Note) 11 12 13 14 15 16 17 18 19 20 : Photo sensor GND VDSUB H1 RD VSS GND RG Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 Symbol V4 V3 V2 SUB GND V1 VL GND VDD VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock GND Vertical register transfer clock Protective transistor bias GND Output circuit supply voltage Signal output Pin No. 11 12 13 14 15 16 17 18 19 20 Symbol VGG VDSUB VSS GND GND RD RG NC H1 H2 Horizontal register transfer clock Horizontal register transfer clock Description Output circuit gate bias Substrate bias circuit supply voltage Output circuit source GND GND Reset drain bias Reset gate clock VGG -2- H2 NC V4 1 VL ICX039DLA Absolute Maximum Ratings Item Substrate clock SUB - GND Supply voltage VDD, VRD, VDSUB, VOUT, VSS - GND VDD, VRD, VDSUB, VOUT, VSS - SUB V1, V2, V3, V4 - GND V1, V2, V3, V4 - SUB Ratings -0.3 to +50 -0.3 to +18 -55 to +10 -15 to +20 to +10 to +15 to +17 -17 to +17 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +30 -30 to +80 -10 to +60 Unit V V V V V V V V V V V V C C 1 Remarks Clock input voltage Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - V4 RG, VGG - GND RG, VGG - SUB VL - SUB Pins other than GND and SUB - VL Storage temperature Operating temperature 1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%. -3- ICX039DLA Bias Conditions 1 [when used in substrate bias internal generation mode] Item Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate clock Symbol VDD VRD VGG VSS VL VDSUB SUB 14.55 Min. 14.55 14.55 1.75 Typ. 15.0 15.0 2.0 1 15.0 2 15.45 V Max. 15.45 15.45 2.25 Unit V V V VRD = VDD Remarks Grounded with 390 resistor 1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. (When CXD1267AN is used.) 2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Output circuit supply voltage Reset drain voltage Output circuit gate voltage Output circuit source Protective transistor bias Substrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision Symbol VDD VRD VGG VSS VL VDSUB VSUB VSUB 6.0 -3 Min. 14.55 14.55 1.75 Typ. 15.0 15.0 2.0 Max. 15.45 15.45 2.25 Unit V V V VRD = VDD Remarks Grounded with 390 resistor 3 4 14.0 +3 V % 5 5 3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. (When CXD1267AN is used.) 4 Connect to GND or leave open. 5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is 3%. However, this setting value has not significance when used in substrate bias internal generation mode. VSUB code -- one character indication Code and optimal setting correspond to each other as follows. VSUB code E f G h J K L m N P Q R S T U V W Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0 DC Characteristics Item Output circuit supply current Symbol IDD Min. Typ. 5.0 -4- Max. 10.0 Unit mA Remarks ICX039DLA Clock Voltage Conditions Item Readout clock voltage VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage | VVH1 - VVH2 | VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage1 VH VHL VRGL VRG VRGLH - VRGLL Substrate clock voltage VSUB 23.0 24.0 4.5 4.75 -0.05 5.0 0 1 5.0 -0.25 -0.25 Symbol Min. Typ. Max. Unit 14.55 15.0 15.45 -0.05 -0.2 0 0 0.05 0.05 -8.5 V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks -9.6 -9.0 8.3 9.0 9.65 Vp-p 0.1 0.1 0.1 0.5 0.5 0.5 0.5 V V V V V V V 5.25 Vp-p 0.05 V V 5.5 Vp-p 0.8 V 25.0 Vp-p 1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications. Item Reset gate clock voltage Symbol VRGL VRG Min. Typ. Max. Unit -0.2 8.5 0 9.0 0.2 V Waveform diagram 4 4 Remarks 9.5 Vp-p -5- ICX039DLA Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Symbol CV1, CV3 CV2, CV4 CV12, CV34 CV23, CV41 CH1 CH2 CHH CRG CSUB R1, R2, R3, R4 RGND Min. Typ. 1800 2200 450 270 64 62 47 8 400 68 15 Max. Unit Remarks pF pF pF pF pF pF pF pF pF V1 CV12 V2 R1 R2 H1 H2 CHH CV23 CH1 CH2 CV1 CV41 CV2 CV4 R4 RGND CV34 CV3 R3 V4 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit -6- ICX039DLA Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II VVT M M 2 10% 0% tr twh tf 0V (2) Vertical transfer clock waveform V1 VVHH V3 VVHH VVHH VVHL VVHL VVH3 VVHH VVHL VVH1 VVH VVHL VVH VVL1 VVLH VVL3 VVLH VVLL VVL VVL VVLL V2 VVHH VVHH V4 VVH VVHH VVHH VVH VVHL VVH2 VVHL VVHL VVH4 VVHL VVL2 VVLH VVLH VVLL VVL VVL4 VVLL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) -7- ICX039DLA (3) Horizontal transfer clock waveform tr twh tf 90% VH 10% VHL twl (4) Reset gate clock waveform tr twh tf VRGH twl Point A RG waveform VRGLH VRGL VRGLL VRG VRGL + 0.5V H1 waveform +2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL -8- ICX039DLA (5) Substrate clock waveform 100% 90% M VSUB 10% 0% M 2 tf VSUB tr twh Clock Switching Characteristics Item Readout clock Vertical transfer clock Horizontal transfer clock Symbol VT V1, V2, V3, V4 H twh twl tr tf Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 0.5 15 20 5.38 5.38 11 13 51 20 15 0.01 0.01 3 0.5 19 15 0.01 0.01 3 0.5 Unit Remarks s During readout 250 ns 19 ns s ns s 1 2 During imaging During parallel- H1 serial H2 conversion RG SUB Reset gate clock Substrate clock 1.5 1.8 During drain charge 1 When vertical transfer clock driver CXD1267AN is used. 2 tf tr - 2ns. Item Horizontal transfer clock Symbol H1, H2 two Min. 16 Typ. 20 Max. Unit ns Remarks 3 3 The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. -9- ICX039DLA Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Flicker Lag Symbol S Vsat Sm SH Vdt Vdt F Lag Min. 500 720 0.00032 0.00056 20 25 2 1 2 0.5 Typ. 600 Max. Unit mV mV % % % mV mV % % Measurement method 1 2 3 4 4 5 6 7 8 (Ta = 25C) Remarks Ta = 60C Zone 0 and I Zone 0 to II' Ta = 60C Ta = 60C Zone Definition of Video Signal Shading 752 (H) 12 12 8 H 8 V 10 H 8 582 (V) Zone 0, I Zone II, II' V 10 6 Ignored region Effective pixel region - 10 - ICX039DLA Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (When used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs x 250 50 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 x x x 100 [%] (1/10V method conversion value) 10 200 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/200 x 100 [%] - 11 - ICX039DLA 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (Vf [mV]). Then substitute the value into the following formula. F = (Vf/200) x 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) x 100 [%] FLD V1 Light Strobe light timing Signal output 200mV Output Vlag (lag) - 12 - Drive Circuit 1 (substrate bias internal generation mode) 15V 1 20 19 18 17 16 15 14 13 22/16V 1M 12 11 1/35V 1 100k 2 3 4 XSUB 5 XV2 6 CXD1267AN -9V 3.3/16V XV1 7 XSG1 8 XV3 9 XSG2 10 XV4 0.01 8 9 10 3.3/20V 22/20V 12 3 4 5 6 7 V4 V3 V2 V1 SUB GND VDD VL GND GND GND Vss 390 0.01 180k 100 1/ 6.3V ICX039DLA (BOTTOM VIEW) H2 H1 NC RG RD H1 20 19 18 17 16 15 14 13 12 11 47/ 6.3V H2 VDSUB VGG 27k VOUT - 13 - 0.01 [A] CCD OUT 3.9k ICX039DLA RG Drive Circuit 2 (substrate bias external adjustment mode) 15V 15k 270k 47k 15k 0.1 -9V 3.3/16V 22/16V 1M 0.1 39k 1/35V 20 19 18 1/35V 100k 27k 1/35V 17 16 15 14 13 12 11 0.1 56k 1 2 3 XSUB 4 XV2 5 XV1 6 CXD1267AN XSG1 7 8 XV3 9 XSG2 XV4 10 22/20V 12 3 4 5 6 7 8 9 10 3.3/20V 0.01 V4 V3 V2 V1 VL SUB GND GND VDD GND Vss VDSUB 390 0.01 ICX039DLA (BOTTOM VIEW) H2 H1 NC RG RD H1 20 19 18 17 16 15 14 13 12 11 47/ 6.3V H2 GND 180k 100 VGG 1/ 6.3V 27k VOUT - 14 - 0.01 [A] CCD OUT 3.9k ICX039DLA RG ICX039DLA Spectral Sensitivity Characteristics (Includes lens characteristics, excludes light source characteristics) 1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart V1 V2 Odd Field V3 V4 1.5 33.6 0.2 V1 V2 Even Field V3 V4 2.5 2.6 2.5 2.5 unit: s - 15 - Drive Timing Chart (Vertical Sync) FLD VD BLK HD 10 15 20 25 320 325 620 625 1 2 3 4 5 310 315 330 335 - 16 - 24 6 135 246 135 582 581 V1 V2 V3 V4 CCD OUT 581 582 135 24 6 135 246 340 ICX039DLA Drive Timing Chart (Horizontal Sync) HD BLK H1 1 2 3 5 10 10 40 20 22 1 2 3 1 2 3 20 H2 10 745 - 17 - RG V1 V2 V3 V4 SUB 750 752 1 3 5 20 30 ICX039DLA ICX039DLA Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Upper ceramic 39N 29N 29N 0.9Nm Lower ceramic Low melting point glass Shearing strength Tensile strength Torsional strength Compressive strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the ceramic portions. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 18 - ICX039DLA c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to other locations as a precaution. d) The upper and lower ceramic are joined by low melting point glass. Therefore, care should be taken not to perform the following actions as this may cause cracks. * Applying repeated bending stress to the outer leads. * Heating the outer leads for an extended period with a soldering iron. * Rapidly cooling or heating the package. * Applying any load or impact to a limited portion of the low melting point glass using tweezers or other sharp tools. * Prying at the upper or lower ceramic using the low melting point glass as a fulcrum. Note that the same cautions also apply when removing soldered products from boards. e) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. - 19 - Package Outline Unit: mm 20pin DIP (600mil) 0 to 9 A (1.0) 11 (R0.7) 1.4 20 (1.7) 11 0.7 9.0 20 ~ 3 C 15.24 1.4 11.55 ~ 3 7.55 V H 15.1 0.3 0.55 B' 0.4 0.7 3.4 0.3 14.6 3 1. "A" is the center of the effective image area. 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package is the height reference. 4. The center of the effective image area, relative to "B" and "B'" is (H, V) = (9.0, 7.55) 0.15mm. 0.83 1.27 1.778 0.46 4.0 0.3 0.4 0.8 0.3 M 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 60m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notch and the hole on the bottom must not be used for reference of fixing. PACKAGE STRUCTURE PACKAGE MATERIAL Cer-DIP LEAD TREATMENT TIN PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 2.6g ICX039DLA 0.25 1 18.0 0.4 17.6 10 10 1 (4.0) B - 20 - ~ |
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